Access IC Lab Receives Best Paper Award at 2017 VLSI-DAT Symposium
Led by Prof. An-Yeu (Andy) Wu (吳安宇), the Access IC Lab of the NTU Graduate Institute of Electronics Engineering (GIEE) won the Best Paper Award at the 2017 IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT). Prof. Wu of NTU GIEE has been working with Assistant Professor Tsung-Te Liu (劉宗德), PhD students Ting-Sheng Chen (陳庭笙) and Ding-Yuan Lee (李鼎元), and MS student Chia-Heng Wu (吳佳衡) in the lab to realize a real-time learning and classification system. The awarded paper, “Low-Latency Voltage-Racing Winner-Take-All (VR-WTA) Circuit for Acceleration of Learning Engine,” was selected among the 34 accepted technical papers presented at the 2017 IEEE VLSI-DAT Symposium. Winning the award demonstrated NTU’s leading role and research capability in the state-of-the-art field of hardware acceleration for machine learning engines.
What is VLSI-DAT Symposium?
The VLSI-DAT Symposium is an international conference on advanced semiconductor technology. The program for the 2017 VLSI-DAT Symposium featured three joint plenary sessions and two joint invited sessions (held with the VLSI-TSA Symposium). Nearly 1,000 members from the academia, industry, and industrial research centers around the globe gathered at the 2017 VLSI-DAT Symposium to share their views on future technology trends and to present papers on their research results. The presented papers were solicited through an open process and selected from all the submitted papers through a blind-review process. The symposium committee evaluated the 34 presented papers in terms of their content, writing, and presentation quality before selecting the Best Paper Award winner. As the award winner, Access IC Lab proposed a new mechanism to improve the performance of real-time classification for neural network computation, bridging the performance gap between existing technology and the future field of artificial intelligence.
Low-Latency Voltage-Racing Winner-Take-All Circuit Accelerates Learning Engines
With the development of machine learning and deep learning, real-time classification and learning have gradually become a major topic. In recent years, researchers have proposed many neural-network hardware acceleration designs, using the analog or digital approach to design the hardware architectures. However, neither approach can achieve high throughput, low latency, and high resolution simultaneously. In light of this, Access IC Lab adopted both the analog and digital approaches in the proposed low-latency VR-WTA circuit to solve the problem of real-time learning and classification operation. This architecture can assist neural networks with parallel comparison, thus substantially increasing the speed of operation to meet the requirement of real-time learning and classification.
In addition, the power consumption is an important consideration for the design of machine learning systems. The proposed architecture terminates the loser at an early stage, and thus eases the burden of system power consumption.
(Source: Access IC Lab, NTU GIEE)