Date: 2017/8/21

NTU Team Wins Second Place at 2017 ACM ISPD Contest

The Association for Computing Machinery (ACM) International Symposium on Physical Design (ISPD) in 2017 was held in Portland in the United States. During the event, the organizer announced the winners of its annual contest, titled “Clock-Aware FPGA Placement ” and sponsored by Xilinx, Inc. this year. While the first place went to the University of Texas at Austin, the NTU team led by professors of electrical and electronic engineering won the second place for developing NTUfplace, a field-programmable gate array (FPGA) placement.

Among the past 13 ACM ISPD Contests, the NTU team led principally by Prof. of Electrical Engineering Yao-Wen Chang (張耀文) has participated in 11 ones and achieved an outstanding winning record (1st place three times and 2nd, 3rd, and 4th places twice each) that makes it the top winner of the ACM ISPD Contest worldwide, followed by the University of Texas at Austin and the University of Michigan at Ann Arbor.

Held by the world-renowned ACM, the ACM SPID Contest is the most established and famous contest on electronic design automation (EDA) around the globe. R. Colin Johnson, a senior technology editor at EE Times and winner of the Kyoto Prize in Journalism in 2010, described the contest as follows: “The best engineering minds on the planet compete each year in the ACM’s ISPD design contest, which was won this year by the National Taiwan University” (2015/04/06, EE Times).

Prof. Chang and his team’s achievements in EDA have been recognized internationally and reported by R. Colin Johnson as follows: “Taiwan’s success so far has been in large part due to electronic design automation (EDA) expertise, where has only been outperformed by the U.S. for the last five years . . . Yao-Wen Chang is typical at NTU, a microelectronics pioneer in EDA, due to receive four separate awards at DAC 2013’s 50th anniversary celebration next month, all related to his unstoppable stream of DAC research papers presenting deep insights into EDA” (2013/05/15, EE Times).

The first ACM ISPD Contest was held in 2005. In general, the company sponsoring the contest for the year announces a topic in December, and the participating teams submit their R&D results and systems in the next March for the company to test. Finally, the year’s winners are announced at the annual ACM ISPD symposium in April. All the chosen topics are crucial and relevant to the physical design process for integrated circuits, including placement, global routing, clock network synthesis, and gate sizing. The contest has attracted exceptional research teams worldwide to develop solutions for the most challenging physical design problems currently facing the industry and academia.

The ACM ISPD Contest is a grand event for the EDA community, attracting immense interest from both the industry and academia. The topic for 2017, “Clock-Aware FPGA Placement,” challenges the contestants to design a clock-aware FPGA placement system that places millions of given circuit elements in the optimal positions on an FPGA chip so as to enable fastest connections, meet timing constraints, and fulfil the industry’s demand for low power consumption. The developed systems’ performance was evaluated using Vivado Design Suite, a program developed by Xilinx. This event was covered by R. Colin Johnson in the article “ISPD Predicts Chip Futures ” on EE Times (2017/04/06).

The NTU team’s outstanding achievements in the ACM ISPD Contest have brought exceptional academic reputation and international visibility to NTU. As circuit placement is currently one of the most discussed topics in the EDA community, each of the three major EDA-related international symposiums (i.e., ACM ISPD, ACM/IEEE DAC, and IEEE/ACM ICCAD) holds its own placement R&D contest. Prof. Chang’s team has been the team to have presented the most papers at the three symposiums, as well as the only contestant to have won the first place in all the three contests. In addition, Prof. Chang’s team is the second team from Taiwan to have received the Best Paper Award of the Design Automation Conference (DAC) after the award first went to a Taiwanese team in 1988. These accomplishments have demonstrated NTU’s leading role in the EDA field worldwide.

  • NTUfplace team members

    (From left) NTUfplace team members: Chau-Chin Huang (黃朝琴), Shih-Chun Chen (陳士鈞), Prof. Sy-Yen Kuo (郭斯彥), Prof. Yao-Wen Chang (張耀文), Yun-Chih Kuo (郭玧質), and Chun-Han Chiang (蔣君涵)

  • Second place award certificate for the NTUfplace team

    Second place award certificate for the NTUfplace team

  • The circuit placement test results include over 900 thousand circuit elements (color dots) and over 900 thousand signal traces (not shown in this figure), and different colors indicate circuit elements in different sequences.

    The circuit placement test results include over 900 thousand circuit elements (color dots) and over 900 thousand signal traces (not shown in this figure), and different colors indicate circuit elements in different sequences.

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